(1) Field of the Invention
This invention relates to packages for encapsulating one or more semiconductor devices, and more particularly to a method for the assembly on a no-lead package having exceptional thermal performance.
(2) Description of the Related Art
In lead frame based semiconductor packages, electrical signals are transmitted between at least one semiconductor device (die) and external circuitry, such as a printed circuit board, by an electrically conductive lead frame. The lead frame includes a number of leads, each having an inner lead end and an opposing outer lead end. Inner lead ends are electrically interconnected to input/output (I/O) pads on the die and outer lead ends provide terminals outside the package body for interconnection to external circuitry. When the outer lead end terminates at the face of the package body, the package is known as a “no lead” package. If the outer leads extend beyond the package body perimeter, the package is referred to as “leaded.” Examples of well known no-lead packages include quad flat no lead (QFN) packages which have four sets of leads disposed around the perimeter of the bottom of a square package body and dual flat no lead (DFN) packages which have two sets of lead disposed along opposite sides of the bottom of a package body. Interconnection of the die to the inner lead ends is typically performed using wire bonding, tape automated bonding (TAB) or flip chip bonding. In wire bonding or TAB bonding, the inner lead ends terminate a distance from the die and are electrically interconnected to I/O pads on an electrically active face of the die by small diameter wires or conductive tape. The die may be supported by a die pad which is surrounded by the leads. In flip chip bonding, the inner lead ends of the lead frame extend beneath the die and the die is flipped so that the I/O pads on the electrically active face of the die contact the inner lead ends by a direct electrical contact, such as a solder joint.
A representative QFN package and its method of manufacture is more fully disclosed in commonly owned U.S. patent application Ser. No. 10/563,712 published as PCT International Application No. WO2005/017968 A2 on Feb. 24, 2005. The disclosure of U.S. patent application Ser. No. 10/563,712 is incorporated by reference in its entirety herein.
An ongoing objective for the designers of no lead semiconductor packages is better thermal management. That is, the ability to remove heat from the electrically active semiconductor die. The QFN is one of the best lead frame based packages in terms of thermal management and cost, but as integrated circuit devices become more complex, there is a need for improved thermal and electrical performance. Among the options available in the market are the use of heavy wires and metal ribbons to conduct heat away from the integrated circuit die.
The use of a heat spreader in a leaded package is disclosed in U.S. Pat. No. 5,608,267 to Mahulikar et al. The use of the heat spreader with a substrate based package is disclosed in U.S. Pat. Nos. 5,977,626 to Wang et al. and 6,432,749 to Libres. The disclosures of U.S. Pat. Nos. 5,608,267; 5,977,626 and 6,432,749 are all incorporated by reference in their entireties herein.
None of the prior art designs include a no-external lead, lead frame based package having a heat spreader. Such a package would have enhanced thermal performance as compared to the QFN and other no-lead type packages presently known.